UIUC / Northeastern
Boston
5
Followers
7
Following
9
Public Repos
0
Private Repos
Language Breakdown
Lines of code distribution across 9 owned repositories
85.8M
Total LOC
VHDL
65,589,672 lines
76.5%
N/A
Verilog
11,452,510 lines
13.4%
N/A
SystemVerilog
3,329,361 lines
3.9%
N/A
Jupyter Notebook
3,033,001 lines
3.5%
N/A
Coq
701,273 lines
0.8%
N/A
Other
1,659,935 lines
1.9%
N/A
I
I-Shaped Developer
I-shapedSpecialist — deep expertise in VHDL
VHDL
Verilog
SystemVerilog
Jupyter Notebook
Coq
Collaboration Network
Global Impact visualization
Repos
10
PRs
0
Growth
+18%
Top Collaborators
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Coding Streak
Contribution activity over the past year
1 day
10
Contributions
9
Commits
0
Pull Requests
Jun
Jul
Aug
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Oct
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Based on GitHub activity
Less
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Following
7 total
Sameer Mallik
@smallik1029
Sakshi Vikas Nikam
@SAKSHINIKAM23
Vyas Raina
@rainavyas
Pradyun Narkadamilli
@pradyungn
nebu
@nebhrajani-a
Synced via GitHub
Top Repositories
Image_to_COE
Convert a Image to a COE file for Vivado
9
0
Python
ProtocolLLM
ProtocolLLM: RTL Benchmark for SystemVerilog Code Generation of Communication Protocols
6
1
SystemVerilog
2048_vivado
This is a System Verilog implementation of 2048 in Vivado and Artx A7
3
0
SystemVerilog
CS225_Final_Proj
3
0
C++
Core_Melters
Out of Order Risc-V processor
2
0
SystemVerilog
Object-Tracking-with-FPGA
2
0
VHDL
PDP-11
This is my trial implementation of PDP-11 processor in System Verilog
1
0
Tcl
Work
The repository of the work that I have done
1
0
C++
Lane-Detection-with-Depth
0
0
Jupyter Notebook
Open Source Impact
Contributions to external projects
0 merged PRs
No external contributions found.